Let's start with the EDA acronym. I propose that we adopt "Extremely Disappointing Announcements," which is closer to the truth than the commonly held definition. As "the leading provider of world-wide acronyms to the expanding global Internet Infrastructure Industry," EDA now means what it should. Think about all of the promises that the EDA vendors have made over the last 20 years. The lack of "deserved" valuations on Wall Street is now explained away quite nicely.

The next logical step would be to deal with the obsession that EDA has with industry consortiums and standards bodies. Let's redefine EDAC as "Extended Death by Anemic Consortiums." How about the VSIA? Perhaps, "Virtually Silent in Industry Accomplishments?" (Good thing that Accellera isn't an acronym.) The industry just has to understand that we want EDA products to work with each other, independent of the IEEE (Interested in Extending EDA Equity).

The acronym IP definitely deserves a new definition. While there are several excellent companies providing true "Intellectual Property," most IP companies fall into two classes: those that provide "Insanity Pricing" and those that provide "Internet Promoted" products. The first category covers all of those EDA companies who want to make billions of dollars for something that cost them a few hundred thousand to build (even though we did most of the work). The second category covers all of those companies whose board of directors demanded that "Internet" be placed in their company's boilerplate (instantly solving my 27 million-transistor design problem).

One of the promises of IP reuse was the reduction of Time to Market (TTM). The redefinition of TTM is sure to be a hit: "Try and Try some More." How about TTM for EDA tools? We are still trying to use their tools, languages, and file formats invented BI (Before Internet).

Okay, so what about ASIC? I propose "Always Specified Incompletely by Customer." With this definition, we designers in the trenches are protected from the inability to use EDA's design tools to effectively specify what we need to build in a reasonable amount of time. At least EDA companies will have a better understanding of P&R (Place and Reboot), UDSM (Usability Doesn't Satisfy Me), and recognize the danger to their industry of FPGA (Found Problem, Got Answer), and DSP (Dangerously Superior Performance).

The rest of the problem is resolved by the redefinition of HDL to the more appropriate "Hardly a Design Language." On this same train of thought, RTL becomes "Really Too Late."

As in any revolutionary venture, there will be disagreements. For instance, the classic digital designer is probably okay with CMOS as the rather descriptive "Complementary Metal Oxide Semiconductor." However, those of us who are radio frequency and microwave types will want to redefine CMOS to "Can't Meet Our Speed." (The software engineers will, of course, want their own version, "Crashed My Operating System.")

In spite of these disagreements, I think that we IC designers (Increasingly Confounded) will ultimately benefit from these new definitions that decrease the TAD. We might even see the government set standards-for RBA (Reality Based Acronyms)-if the idea really catches on. But until the two sides agree on their terms, we will have to learn to understand that in "EDAese" SOC still stands for "Suing Our Competitors," rather than "Serving Our Customers," along with market valuations, and the credibility EDA companies deserve.

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